Internal implementation - write all lanes atomically.
461 {
463 FL_WARN(
"MultiLaneDevice: Not ready for write");
464 return WriteResult("Device not ready");
465 }
466
467 if (lane_data.
size() >
pImpl->lanes.size()) {
468 FL_WARN(
"MultiLaneDevice: Too many lanes provided (" << lane_data.
size() <<
" > " <<
pImpl->lanes.size() <<
")");
469 return WriteResult("Too many lanes provided");
470 }
471
472
473 if (lane_data.
size() > 1) {
474 size_t first_size = lane_data[0].
size();
475 for (
size_t i = 1; i < lane_data.
size(); i++) {
476 if (lane_data[i].size() != first_size) {
477 FL_WARN(
"MultiLaneDevice: Lane size mismatch - lane 0 has " << first_size <<
" bytes, lane " << i <<
" has " << lane_data[i].size() <<
" bytes");
478 return WriteResult("Lane size mismatch: all lanes must have identical sizes");
479 }
480 }
481 }
482
483
485
486
487 for (
size_t i = 0; i < lane_data.
size(); i++) {
488 pImpl->lanes[i].write(lane_data[i].data(), lane_data[i].size());
489 }
490
491
492 auto flush_result =
flush();
493 if (!flush_result.ok()) {
494 FL_WARN(
"MultiLaneDevice: Flush failed");
495 return WriteResult("Flush failed");
496 }
497
498 FL_DBG(
"MultiLaneDevice: Wrote " << lane_data.
size() <<
" lanes atomically (async)");
499
500
501 return WriteResult();
502}
constexpr fl::size size() const FL_NO_EXCEPT
bool waitComplete(u32 timeout_ms=(fl::numeric_limits< u32 >::max)()) FL_NO_EXCEPT
Wait for pending transmission to complete.
Result< void > flush() FL_NO_EXCEPT
Flush all lanes (transpose and transmit)
fl::unique_ptr< Impl > pImpl
bool isReady() const FL_NO_EXCEPT
Check if device is initialized.