86 {
88
89
90 return true;
91 }
94 return true;
95 }
98 if (d_hi < d_lo) {
99 return false;
100 }
101 for (fl::u32 d = d_lo; d <= d_hi; ++d) {
102 if (d == 0u) {
103 continue;
104 }
105 fl::u32 effective_clock = cap.
base_clock_hz /
static_cast<fl::u32
>(d);
106 if (effective_clock == 0u) {
107 continue;
108 }
113 return true;
114 }
115 }
116 return false;
117}
bool canHitPhase(fl::u32 effective_clock_hz, fl::u16 max_ticks, const NanosRange &window) FL_NO_EXCEPT
fl::u32 base_clock_hz
e.g. 80'000'000 for RMT5 (APB_CLK)
fl::u16 max_divider
largest divider -> coarsest tick width
constexpr bool isUnspecified() const FL_NO_EXCEPT
fl::u16 max_phase_ticks
counter-width cap per phase
fl::u16 min_divider
smallest divider -> finest tick width
constexpr bool isUnspecified() const FL_NO_EXCEPT