FastLED 3.10.6
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◆ isClocklessTimingCompatible()

bool fl::can_match_detail::isClocklessTimingCompatible ( const ClocklessTimingCapability & cap,
const ChipsetClocklessTiming & chip )
inline

Definition at line 84 of file can_match.cpp.hpp.

86 {
87 if (cap.isUnspecified()) {
88 // Driver doesn't constrain timing — treat as "any chipset fits"
89 // (e.g. DMA-fed pattern shifters where any tick width is OK).
90 return true;
91 }
94 return true;
95 }
96 fl::u16 d_lo = cap.min_divider == 0u ? 1u : cap.min_divider;
97 fl::u16 d_hi = cap.max_divider == 0u ? d_lo : cap.max_divider;
98 if (d_hi < d_lo) {
99 return false;
100 }
101 for (fl::u32 d = d_lo; d <= d_hi; ++d) {
102 if (d == 0u) {
103 continue;
104 }
105 fl::u32 effective_clock = cap.base_clock_hz / static_cast<fl::u32>(d);
106 if (effective_clock == 0u) {
107 continue;
108 }
109 if (canHitPhase(effective_clock, cap.max_phase_ticks, chip.t0h_window) &&
110 canHitPhase(effective_clock, cap.max_phase_ticks, chip.t0l_window) &&
111 canHitPhase(effective_clock, cap.max_phase_ticks, chip.t1h_window) &&
112 canHitPhase(effective_clock, cap.max_phase_ticks, chip.t1l_window)) {
113 return true;
114 }
115 }
116 return false;
117}
bool canHitPhase(fl::u32 effective_clock_hz, fl::u16 max_ticks, const NanosRange &window) FL_NO_EXCEPT
fl::u32 base_clock_hz
e.g. 80'000'000 for RMT5 (APB_CLK)
fl::u16 max_divider
largest divider -> coarsest tick width
constexpr bool isUnspecified() const FL_NO_EXCEPT
fl::u16 max_phase_ticks
counter-width cap per phase
fl::u16 min_divider
smallest divider -> finest tick width
constexpr bool isUnspecified() const FL_NO_EXCEPT

References canHitPhase(), and fl::FL_NO_EXCEPT.

Referenced by checkOneGroup().

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