Identify the channel's final current/quantization choice without adding a virtual slot or storage to every ordinary CLEDController.
175 {
178 for (fl::size i = 0; i < registered.
size(); ++i) {
184 if (
spi ==
nullptr)
return policy;
185 switch (
spi->timing.chipset) {
188 break;
191 break;
199 spi->timing.chipset, profile !=
nullptr
204 break;
205 }
206 default:
207 break;
208 }
209 return policy;
210 }
211
212
213 return policy;
214}
CLEDController * controller
static fl::vector< fl::ChannelPtr > & channels() FL_NO_EXCEPT
stored ChannelPtrs to keep them alive
const EmitterProfile * emitterProfile() const FL_NO_EXCEPT
const ChipsetVariant & getChipset() const FL_NO_EXCEPT
Get the chipset configuration variant.
LED channel for parallel output, pretty much a CPixelLEDController but with timing and pin informatio...
fl::size size() const FL_NO_EXCEPT
u8 & hdFieldFloor() FL_NO_EXCEPT
Backing store for CFastLED::setHdFieldFloor().
u8 hdMinimumField(FiveBitSemantics semantics, u8 floor_setting) FL_NO_EXCEPT
The lowest field the managed HD path may choose: the configured flicker floor for a secondary slow-PW...
@ LPD6803
LPD6803 LED chipset.
@ APA102HD
APA102 LED chipset with 5-bit gamma correction.
@ DOTSTARHD
APA102HD LED chipset alias.
@ SK9822HD
SK9822 LED chipset with 5-bit gamma correction.
@ LPD8806
LPD8806 LED chipset.
@ HD107HD
Same as APA102HD, but in turbo 40-mhz mode.
FiveBitSemantics fiveBitSemanticsFor(SpiChipset chip, FiveBitSemantics profile) FL_NO_EXCEPT
The 5-bit semantics for chip, with profile overriding the chip's default when it is not NotApplicable...
SPI chipset configuration (data + clock pins)
FiveBitSemantics five_bit_semantics