FastLED 3.9.15
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config.h
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1#pragma once
2
5
6#include "fl/stl/stdint.h"
7#include "fl/stl/vector.h"
8#include "fl/stl/span.h"
9#include "fl/stl/noexcept.h"
10
11namespace fl {
12
13// ============================================================================
14// SPI Constants
15// ============================================================================
16
18constexpr size_t MAX_SPI_LANES = 32;
19
20// ============================================================================
21// SPI Output Modes
22// ============================================================================
23
31
38
39// ============================================================================
40// SPI Configuration
41// ============================================================================
42
44struct SpiConfig {
46
48 SpiConfig(int clk, int data, u32 speed_hz = 0xffffffff, spi_output_mode_t output_mode = spi_output_mode_t::SPI_AUTO, u8 spi_mode = 0)
49 : clock_pin(clk)
50 , clock_speed_hz(speed_hz)
53 data_pins.push_back(data);
54 }
55
58 : clock_pin(clk)
59 , clock_speed_hz(speed_hz)
62 // Manually copy pins to data_pins vector
63 for (size_t i = 0; i < pins.size(); i++) {
64 data_pins.push_back(pins[i]);
65 }
66 }
67
69 bool isMultiLane() const { return data_pins.size() > 1; }
70
73 u32 clock_speed_hz = 0xffffffff;
76};
77
78namespace spi {
79
80// Use the top-level SpiConfig as the internal Config
81// This avoids duplication and ensures consistency
83
84} // namespace spi
85} // namespace fl
int pins[]
Definition Spi.ino:11
fl::SpiConfig Config
Definition config.h:82
unsigned char u8
Definition stdint.h:131
spi_output_mode_t
SPI output mode for multi-lane devices.
Definition config.h:25
@ SPI_HW
Use DMA-capable hardware (Async or Sync), supports 1/2/4/8 lanes depending on platform.
Definition config.h:27
@ SPI_AUTO
Auto-selects best backend (DMA/bit-bang/ISR)
Definition config.h:26
@ SPI_ISR
Use ISR-based software (Async)
Definition config.h:29
@ SPI_BITBANG
Use bit-bang software (Blocking)
Definition config.h:28
constexpr size_t MAX_SPI_LANES
Maximum number of SPI lanes supported (hardware: 1-8, software: up to 32)
Definition config.h:18
@ AUTO
Sentinel: defer to DefaultBus<Chipset>::value.
Definition bus.h:61
SpiParallelMode
Parallel device execution modes.
Definition config.h:33
@ BITBANG_BLOCKING
Bit-bang blocking mode.
Definition config.h:36
@ ISR_ASYNC
ISR-driven async mode.
Definition config.h:35
Base definition for an LED controller.
Definition crgb.hpp:179
#define FL_NOEXCEPT
u32 clock_speed_hz
Clock frequency in Hz (0xffffffff = as fast as possible)
Definition config.h:73
SpiConfig() FL_NOEXCEPT=default
int clock_pin
SCK pin number.
Definition config.h:71
spi_output_mode_t output_mode
Output mode (auto/hw/bitbang/isr)
Definition config.h:74
fl::vector< int > data_pins
Data pins (1 = single-lane, 2-8 = multi-lane)
Definition config.h:72
bool isMultiLane() const
Check if this is a multi-lane configuration.
Definition config.h:69
SpiConfig(int clk, fl::span< const int > pins, u32 speed_hz=0xffffffff, spi_output_mode_t output_mode=spi_output_mode_t::SPI_AUTO, u8 spi_mode=0)
Construct multi-lane SPI config.
Definition config.h:57
u8 spi_mode
SPI mode 0-3 (CPOL/CPHA)
Definition config.h:75
Configuration for SPI device (supports 1-8 lanes)
Definition config.h:44