63 for (
size_t i = 0; i <
pins.size(); i++) {
spi_output_mode_t
SPI output mode for multi-lane devices.
@ SPI_HW
Use DMA-capable hardware (Async or Sync), supports 1/2/4/8 lanes depending on platform.
@ SPI_AUTO
Auto-selects best backend (DMA/bit-bang/ISR)
@ SPI_ISR
Use ISR-based software (Async)
@ SPI_BITBANG
Use bit-bang software (Blocking)
constexpr size_t MAX_SPI_LANES
Maximum number of SPI lanes supported (hardware: 1-8, software: up to 32)
@ AUTO
Sentinel: defer to DefaultBus<Chipset>::value.
SpiParallelMode
Parallel device execution modes.
@ BITBANG_BLOCKING
Bit-bang blocking mode.
@ ISR_ASYNC
ISR-driven async mode.
Base definition for an LED controller.
u32 clock_speed_hz
Clock frequency in Hz (0xffffffff = as fast as possible)
SpiConfig() FL_NOEXCEPT=default
int clock_pin
SCK pin number.
spi_output_mode_t output_mode
Output mode (auto/hw/bitbang/isr)
fl::vector< int > data_pins
Data pins (1 = single-lane, 2-8 = multi-lane)
bool isMultiLane() const
Check if this is a multi-lane configuration.
SpiConfig(int clk, fl::span< const int > pins, u32 speed_hz=0xffffffff, spi_output_mode_t output_mode=spi_output_mode_t::SPI_AUTO, u8 spi_mode=0)
Construct multi-lane SPI config.
u8 spi_mode
SPI mode 0-3 (CPOL/CPHA)
Configuration for SPI device (supports 1-8 lanes)