8#include "platforms/shared/spi_bitbang/spi_isr_1.h"
9#include "platforms/shared/spi_bitbang/spi_isr_2.h"
10#include "platforms/shared/spi_bitbang/spi_isr_4.h"
11#include "platforms/shared/spi_bitbang/spi_isr_8.h"
12#include "platforms/shared/spi_bitbang/spi_isr_16.h"
13#include "platforms/shared/spi_bitbang/spi_isr_32.h"
14#include "platforms/shared/spi_bitbang/spi_block_1.h"
15#include "platforms/shared/spi_bitbang/spi_block_2.h"
16#include "platforms/shared/spi_bitbang/spi_block_4.h"
17#include "platforms/shared/spi_bitbang/spi_block_8.h"
18#include "platforms/shared/spi_bitbang/spi_block_16.h"
19#include "platforms/shared/spi_bitbang/spi_block_32.h"
30ParallelDevice::Config::Config()
68 static_cast<SpiIsr1*
>(
backend)->stopISR();
70 static_cast<SpiIsr2*
>(
backend)->stopISR();
72 static_cast<SpiIsr4*
>(
backend)->stopISR();
74 static_cast<SpiIsr8*
>(
backend)->stopISR();
76 static_cast<SpiIsr16*
>(
backend)->stopISR();
78 static_cast<SpiIsr32*
>(
backend)->stopISR();
102 size_t num_pins = gpio_pins.
size();
105 for (
int byte_val = 0; byte_val < 256; byte_val++) {
110 for (
size_t bit_pos = 0; bit_pos < num_pins && bit_pos < 8; bit_pos++) {
111 u32 pin_mask = 1u << gpio_pins[bit_pos];
113 if (byte_val & (1 << bit_pos)) {
114 set_mask |= pin_mask;
116 clear_mask |= pin_mask;
121 for (
size_t pin_idx = 8; pin_idx < num_pins; pin_idx++) {
122 clear_mask |= (1u << gpio_pins[pin_idx]);
125 set_masks[byte_val] = set_mask;
126 clear_masks[byte_val] = clear_mask;
141 if (num_pins == 0 || num_pins > 32) {
142 FL_WARN(
"ParallelDevice: Invalid number of GPIO pins (" << num_pins
143 <<
"), must be 1-32");
146 FL_DBG(
"ParallelDevice: Created with " << num_pins <<
" GPIO pins");
160 if (
pImpl->initialized) {
165 size_t num_pins =
pImpl->config.gpio_pins.size();
168 if (num_pins == 0 || num_pins > 32) {
173 u8 backend_width = 1;
174 if (num_pins > 16) backend_width = 32;
175 else if (num_pins > 8) backend_width = 16;
176 else if (num_pins > 4) backend_width = 8;
177 else if (num_pins > 2) backend_width = 4;
178 else if (num_pins > 1) backend_width = 2;
180 pImpl->backend_width = backend_width;
185 pImpl->is_isr_mode = use_isr;
189 u32 clear_masks[256];
190 buildDefaultLUT(
pImpl->config.gpio_pins, set_masks, clear_masks);
198 FL_DBG(
"ParallelDevice: Initializing ISR mode (width=" << (
int)backend_width <<
")");
202 return fl::task::Error(
"ISR mode not yet implemented for ParallelDevice");
206 FL_DBG(
"ParallelDevice: Initializing bit-bang mode (width=" << (
int)backend_width <<
")");
210 return fl::task::Error(
"Bit-bang mode not yet implemented for ParallelDevice");
213 pImpl->initialized =
true;
226 pImpl->releaseBackend();
228 FL_DBG(
"ParallelDevice: Shutdown complete");
238 "Device not initialized");
241 if (!data || size == 0) {
243 "Invalid data or size");
249 "ParallelDevice::write() not yet implemented");
275 if (!set_masks || !clear_masks) {
276 FL_WARN(
"ParallelDevice: Invalid LUT pointers");
282 FL_DBG(
"ParallelDevice: LUT configuration not yet implemented");
286 static const Config empty_config;
static expected failure(E err, const char *msg=nullptr) FL_NOEXCEPT
Create error result.
bool isReady() const
Check if device is initialized.
~ParallelDevice() FL_NOEXCEPT
Destructor - releases hardware resources.
const Config & getConfig() const
Get current configuration.
Result< Transaction > write(const u8 *data, size_t size)
Write data (single stream drives all pins via LUT)
bool waitComplete(u32 timeout_ms=(fl::numeric_limits< u32 >::max)())
Wait for pending transmission to complete.
void configureLUT(const u32 *set_masks, const u32 *clear_masks)
Configure custom LUT (advanced)
bool isBusy() const
Check if transmission is in progress.
ParallelDevice(const Config &config)
Construct parallel device.
void end()
Shutdown hardware and release resources.
fl::optional< fl::task::Error > begin()
Initialize hardware and setup LUT.
fl::unique_ptr< Impl > pImpl
fl::size size() const FL_NOEXCEPT
Shared implementation helpers for SPI device classes.
Centralized logging categories for FastLED hardware interfaces and subsystems.
void buildDefaultLUT(const fl::vector< u8 > &gpio_pins, u32 *set_masks, u32 *clear_masks)
Build default LUT for parallel GPIO mapping.
fl::result< T, SPIError > Result
fl::enable_if<!fl::is_array< T >::value, unique_ptr< T > >::type make_unique(Args &&... args) FL_NOEXCEPT
@ AUTO
Sentinel: defer to DefaultBus<Chipset>::value.
constexpr nullopt_t nullopt
SpiParallelMode
Parallel device execution modes.
@ ISR_ASYNC
ISR-driven async mode.
@ AUTO
Auto-select best mode (default: ISR)
Base definition for an LED controller.
Parallel GPIO SPI device for 1-32 outputs driven from single data stream.
u32 timer_hz
Timer frequency for ISR mode.
fl::vector< u8 > gpio_pins
GPIO pins (1-32 pins)
SpiParallelMode mode
Execution mode (ISR vs bit-bang)
u8 clock_pin
Clock pin (SCK)
Configuration for parallel GPIO SPI.