152 {
155 }
158 }
161 }
165 }
166 }
167
168
169
170
171
172
173 fl::u32 requested_count = r.
data_pins.count();
174 if (
g.max_concurrent != 0u && requested_count >
static_cast<fl::u32
>(
g.max_concurrent)) {
176 }
179 if (!fr.isUnspecified() && !fr.contains(*r.
frequency_hz)) {
181 }
182 }
186 }
187 }
189}
bool isContiguousBitset(const PinBitset &b) FL_NO_EXCEPT
bool isClocklessTimingCompatible(const ClocklessTimingCapability &cap, const ChipsetClocklessTiming &chip) FL_NO_EXCEPT
FreqRange effectiveFrequencyRange(const DriverCapabilities &caps, const PinGroup &g) FL_NO_EXCEPT
@ NoPinPair
clock pin not in the matching group's allowlist
@ NoProtocol
driver doesn't support the requested Protocol
@ NoPin
data pin not in any matching group's allowlist
@ NoCapacity
group full / driver-total cap reached
@ NoTiming
chipset tolerance windows can't be hit
@ NoFrequency
requested freq outside driver/group range
@ Spi
Data + clock (APA102, SK9822, ...)
@ Clockless
Single data line + async timing (WS2812, SK6812, ...)
ChipsetClocklessTiming timing
unspecified/any for Spi requests
PinBitset data_pins
bit N set = pin N included
fl::i16 clock_pin
-1 for Clockless; single shared clock for Spi
fl::optional< fl::u32 > frequency_hz
mostly SPI override
ClocklessTimingCapability clockless_timing
Clock-tree model — the ONLY chipset-support gate.