FastLED 3.10.6
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◆ checkOneGroup()

HandleResult fl::can_match_detail::checkOneGroup ( const DriverCapabilities & caps,
const PinGroup & g,
const ChannelRequest & r )
inline

Definition at line 149 of file can_match.cpp.hpp.

152 {
153 if (g.protocol != r.protocol) {
155 }
156 if (!g.data_pins.acceptsAll(r.data_pins)) {
157 return HandleResult::NoPin;
158 }
159 if (g.pins_must_be_contiguous && !isContiguousBitset(r.data_pins)) {
160 return HandleResult::NoPin;
161 }
162 if (r.protocol == Protocol::Spi) {
163 if (!g.clock_pins.accepts(r.clock_pin)) {
165 }
166 }
167 // Capacity: bulk requests consume one slot per set bit on this
168 // group (the "ganged into one group" model). For "fan out across
169 // independent groups" the resolver handles distribution at a higher
170 // layer — this free function answers "does THIS group accept the
171 // entire bitset?". Single-pin requests trivially fit (count=1
172 // <= max_concurrent for any sane group).
173 fl::u32 requested_count = r.data_pins.count();
174 if (g.max_concurrent != 0u && requested_count > static_cast<fl::u32>(g.max_concurrent)) {
176 }
177 if (r.frequency_hz.has_value()) {
178 FreqRange fr = effectiveFrequencyRange(caps, g);
179 if (!fr.isUnspecified() && !fr.contains(*r.frequency_hz)) {
181 }
182 }
183 if (r.protocol == Protocol::Clockless) {
186 }
187 }
188 return HandleResult::Yes;
189}
bool isContiguousBitset(const PinBitset &b) FL_NO_EXCEPT
bool isClocklessTimingCompatible(const ClocklessTimingCapability &cap, const ChipsetClocklessTiming &chip) FL_NO_EXCEPT
FreqRange effectiveFrequencyRange(const DriverCapabilities &caps, const PinGroup &g) FL_NO_EXCEPT
@ NoPinPair
clock pin not in the matching group's allowlist
@ NoProtocol
driver doesn't support the requested Protocol
@ NoPin
data pin not in any matching group's allowlist
@ NoCapacity
group full / driver-total cap reached
@ NoTiming
chipset tolerance windows can't be hit
@ NoFrequency
requested freq outside driver/group range
InputGamut g
Definition rgbw.h:124
@ Spi
Data + clock (APA102, SK9822, ...)
@ Clockless
Single data line + async timing (WS2812, SK6812, ...)
ChipsetClocklessTiming timing
unspecified/any for Spi requests
PinBitset data_pins
bit N set = pin N included
fl::i16 clock_pin
-1 for Clockless; single shared clock for Spi
fl::optional< fl::u32 > frequency_hz
mostly SPI override
ClocklessTimingCapability clockless_timing
Clock-tree model — the ONLY chipset-support gate.

References fl::Clockless, fl::FreqRange::contains(), effectiveFrequencyRange(), fl::FL_NO_EXCEPT, fl::g, isClocklessTimingCompatible(), isContiguousBitset(), fl::FreqRange::isUnspecified(), fl::NoCapacity, fl::NoFrequency, fl::NoPin, fl::NoPinPair, fl::NoProtocol, fl::NoTiming, fl::Spi, and fl::Yes.

Referenced by fl::canMatch().

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